1. Field of the Invention
The present invention relates generally to a semiconductor device with a source line and a fabrication method thereof, and more particularly to a nonvolatile semiconductor memory device having a source line and a method of fabricating the same.
2. Description of the Related Art
A description will now be given of a conventional semiconductor device, referring, by way of example, to a NAND-type EEPROM (electrically erasable and programmable read-only memory) that is a kind of nonvolatile semiconductor memory device.
FIG. 1 is a circuit diagram of a conventional NAND-type EEPROM, FIG. 2A is a layout of the NAND-type EEPROM, and FIG. 2B is a cross-sectional view taken along line 2B—2B in the layout of FIG. 2A.
As is shown in FIG. 1, memory cell transistors M0, M1, . . . , M15 are connected in series. Select transistors SGD and SGS are connected to both ends of the series-connected memory cell transistors. A bit line BL is connected to the select transistor SGD, and a source line SL is connected to the select transistor SGS. Word lines WL0, WL1, . . . , WL15 are connected to the gate electrodes of the memory cell transistors M0 to M15, respectively. Select lines SSL and GSL are connected to the gate electrodes of the select transistors SGD and SGS, respectively.
As is shown in FIG. 2A, the word lines WL0 to WL15 and select lines SSL and GSL are arranged in parallel. The bit lines BL are arranged perpendicular to the word lines WL0 to WL15. Bit line contacts BLC are arranged between the select lines SSL.
In the NAND-type EEPROM, as shown in FIG. 2B, a plurality (16 in FIG. 2B) of memory cell transistors M0 to M15 are arranged in series between the bit line contact BLC and source line SL, with the select transistors SGD and SGS interposed.
As a structure of the source line SL in the NAND-type EEPROM, a prior-art document (Jung-Dai Choi, et al.: IEDM Tech. Dig., pp. 767-770 (2000)) discloses a source line structure (local interconnect structure) wherein impurity-doped polysilicon is buried in an insulating film, as shown in FIG. 2B.
However, the above-described conventional method has the following problems.
A first problem is a great height of the source line.
According to the fabrication method disclosed in the aforementioned document, the source line is formed to have a height that is greater than, at least, the height of the gate of the memory cell. On the other hand, in order that the source line may have a sufficiently low resistivity, it is necessary that the source line be formed to have a sufficient height. If the width of the source line decreases in accordance with device miniaturization, the source line needs to be formed with a greater height for compensation of the decrease in width.
To ensure insulation between the source line and bit line, the bit line needs to be formed at a higher position than the source line. Accordingly, the height of the bit line contact increases as the height of the source line increases, and the aspect ratio of the bit line contact increases. As a result, in the prior art, it would be difficult to achieve a satisfactory device yield.
A major factor of the above problem is the use of polysilicon as buried material for forming the source line, the polysilicon having a lower conductivity than a metal or a metal compound.
A second problem is a decrease in lithography margin, e.g. exposure latitude, occurring in a step of patterning a gate electrode. In general, a regular line-and-space pattern is desirable for ensuring a good lithography margin. In the aforementioned prior-art method, however, a wide space needs to be provided for forming the source line between the select transistors. This leads to a pattern irregularity and a decrease in lithography margin such as an exposure latitude.